Chiplets, Advanced Packaging, and the Chips Behind AI
Final presentation from Judd Gerber · Intel · October 8, 2026.
View presentation PDF ↗Talk abstract
Why chiplets are changing processor design
As semiconductor manufacturing pushes against the limits of traditional monolithic chip design, chiplet-based architectures have emerged as a transformative solution for the industry. By breaking complex processors into smaller, discrete dies, manufacturers can significantly improve yields, reduce waste, and circumvent the hard reticle-size limitations imposed by modern lithography machines. This approach also unlocks powerful cost and efficiency advantages, allowing engineers to optimize each functional block by selecting the most appropriate manufacturing node—for example, pairing cutting-edge processes for high-performance logic with more cost-effective nodes for memory and I/O components.
Chiplet architectures, however, have brought renewed focus to the packaging that sits between the silicon die and the system PCB. These packages have had to increase in complexity to support many more chiplet-to-chiplet connections. Today’s advanced packages make it possible to combine specialized CPU, AI, and graphics modules within a single package. The ability to reuse proven chiplet designs and selectively upgrade individual functional blocks without redesigning an entire system represents a shift in how the semiconductor industry approaches processor development.
This talk will explore how chiplet technology is overcoming the manufacturing, economic, and design challenges facing the industry and shaping the future of advanced semiconductor packaging.
Speaker bio
About Judd
Judd Gerber is a Senior Principal Engineer in Sort Test Technology Development within Intel's Advanced Packaging Technology and Manufacturing Group. He holds a Bachelor of Science degree in Electrical Engineering from the University of Idaho and brings over 30 years of test and measurement expertise to his work.
Over the course of his career, Judd has spent 27 years at Intel, where he has held key leadership positions across both Sort Test Technology Development and Logic Technology Development. His broad experience spans the full spectrum of semiconductor testing, including Wafer Sort and Final Test for Packaged Units.
In his current role, Judd leads Sort Development for Intel and serves as the Wafer Sort Factory Manager at Intel's Ronler Acres campus, where he oversees critical testing operations that support Intel's advanced semiconductor manufacturing efforts.
Event archive
October 8 Event Recap
Judd Gerber of Intel joined the Front Range Professional Speaker Series to explain why chiplets and advanced packaging are becoming central to modern computing — from silicon and wafer basics to reticle limits, modular design, yield, cost, and the packaging technologies that make multi-die systems possible.
Event resources
Chiplets: What / Why / Where
Watch the October 8, 2026 presentation by Judd Gerber of Intel.
Watch on YouTube ↗Full event recording · Front Range Professional Speaker Series · CU Boulder